Clock Distribution Optimization Using CCD CTS in a Power-Constrained Design

Abstract

Clock distribution is among the critical considerations in application specific integrated circuit (ASIC) design nowadays, and it is a significant factor in power consumption and timing performance. Clock tree occupies nearly three quarters of the total dynamic power in power-constrained designs, and this implies that it requires some original techniques to optimize it. This paper will discuss a detailed study of the clock distribution optimization in a 28 nm technology node, which is having stringent power limitations, in the Concurrent Clock and Data (CCD) based Clock Tree Synthesis technique. We run our strategy on a high-complexity design block with 65,946 flattened cells and 12,647 hierarchical instances with a clock frequency of 454.5 MHz and clock period of 2.2ns. Through a systematic use of the CCD-CTS methodology, we can demonstrate a massive improvement in the quality measures of clock trees and at a reasonable power cost. We determined that CCD-based CTS achieves clock repeater counts nearly 48 percent less than conventional techniques with clock latency of 0.26 ns and controlled skew of 0.15 ns. The findings demonstrate that CCD-CTS is a useful methodology to employ in the attempt to apply timing closure in power-constrained settings without affecting the quality measures of designs on multiple optimization objectives.