Early Congestion Detection and Mitigation in a Macro-Rich 28nm ASIC Design

Abstract

One of the most important issues of current ASIC physical design, especially the macro-dominated layout, is routing congestion. Congestion related problems are known to be detected at the end of the routing process of many industrial design flows, leading to numerous design cycles, longer turn around time, and timing closure variability. The paper describes a preliminary congestion prediction and mitigation algorithm to a macro-rich 28-nm ASIC architecture. The suggested solution is based on the global routing congestion measures, macro flyline, pin density assessment, and boundary logic allocation to detect the congestion-prone areas before detailed routing. Using the early indicators of congestion to correlate with downstream routing failures and setup timing violations, high-risk regions are identified with high confidence. Specific corrective measures such as refinement of macro placement, redistribution of boundary cells.