Physical DRC Hotspots in Dense ASIC Designs and Their Resolution Strategies

Abstract

Closure of Physical Design Rule Check(DRC) has become a very important issue in advanced 28nm ASIC design because of aggressive scaling, dense layout structure and strict foundry constraints. The dense transistor layout and intricate routing layouts, par- ticularly of high-performance cores and I/O-intensive subunits, are causing repeat failures in DRC, such as violation of minimum spacing, via enclosure failures, non-conformity in metal density, and antenna effects. Multi-layer routing congestion, large via counts, and tight pitch demands are the exacerbating factors of these hotspots, which are caused by the 28nm node. This paper determines the common DRC violations in dense logic and memory-macro interfaces, and introduces an iterative approach to resolution which is layout-legalization of placement, pattern-legalization of routing, selective-layer-promotion, and post-route-optimization using DRC-induced ECOs. The proposed strategies can reduce the number of violations by more than 92 percent when using signoff-quality DRC tools and machine learning-aided hotspot prediction to aid in tapeout-ready designs. The findings indicate that implement the multi-stage DRC closure approach proactively at an early stage during physical implementation is critical to provide manufacturability and yield in 28nm ASICs.