Vol. 7 No. 1 (2026): IJCRL

Articles

• Clock Distribution Optimization Using CCD CTS in a Power-Constrained Design

  Harshith K.S, Gadipelly Dharanidhar, A.S.V.N Anjaneya Seshasai, Vijay Vallabhuni (Author)

  1-24

  • pdf

• Physical DRC Hotspots in Dense ASIC Designs and Their Resolution Strategies

  Vaddu Uday Kiran Reddy, Sayed Huzaifulla Peerzade, A.S.V.N Anjaneya Seshasai, Vallabhuni Vijay (Author)

  25-47

  • pdf

• Early Congestion Detection and Mitigation in a Macro-Rich 28nm ASIC Design

  Gundelli Srikanth, Harsha Vardhan Reddy. G, Srinidhi Prabhakar, Vallabhuni Vijay (Author)

  48-58

  • pdf

• Mitigating Clock Routing Shorts and DRVs in Advanced CTS Implementations

  Pragathi C.U, Telu Meghana, Vallabhuni Vijay, Srinidhi Prabhakar (Author)

  59-82

  • pdf