Mitigating Clock Routing Shorts and DRVs in Advanced CTS Implementations

Abstract

Since the timing closure, power consumption, and system reliability, in general, are directly related to the clock network, the need of robust clock routing of modern advanced-node ASIC design is an essential requirement. Due to aggressive scaling of technology, Clock Tree Synthesis (CTS) is being constrained to work with very dense standard-cell layouts and routing resources, and in fact, routing congestion is greatly increased. Clock wires are commonly squeezed into narrow or irregular paths in the high-density population areas, and this may cause accidental shorts to power rails or signal nets, frequent spacing and enclosure design violations (DRVs) and a decrease in clock performance because of the unnecessary detours and buffering swellings. Traditional CTS flows are biased towards skew and latency optimization, which when not thought of proactively leads to a variety of violations on a variety of different implementation cycles and slow convergence of the design. The paper describes clock routing conflicts which occur because of congestion as a significant cause of chronic shorts and DRVs in advanced CTS systems. A novel mitigation flow, which is built on the root cause identification and uses selective clock rerouting and hot spot sensitive adaptive Non-Default Rules (NDRs), is suggested to solve the problem. Following global routing, routing hotspots are determined and they are marked as clock-protected zones. Only affected clock segments are compelled to spacing and via enclosure requirements in such areas. According to the outcomes of the experiment, this targeted approach preserves the total ability of routes, clock skew, power-performance- area (PPA) metrics, and reduces shortages and DRVs due to clocks by a substantial factor.